? semiconductor components industries, llc, 2002 may, 2002 rev. 4 1 publication order number: mc100lve164/d mc100lve164 3.3vecl 16:1 multiplexer the mc100lve164 is a 16:1 multiplexer with a differential output. the select inputs (sel0, 1, 2, 3 ) control which one of the sixteen data inputs (a0 a15) is propragated to the output. the device is functionally equivalent to the mc100e164 except it operates from a 3.3 v supply. the device is packaged in the 32lead lqfp. the lqfp has a 7x7 mm body with a 0.8 mm lead pitch. special attention to the design layout results in a typical skew between the 16 inputs of only 50 ps. ? 850 ps data input to output ? differential output ? esd protection: >2 kv hbm, >200 v mm ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.8 v ? internal input pulldown resistors ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 2 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 307 devices lqfp fa suffix case 873a device package shipping ordering information mc100lve164fa lqfp 250 units/tray marking diagram* mc100lve164far2 lqfp 2000 tape & reel *for additional information, see application note and8002/d mc100lve awlyyww 1 32 a = assembly location wl = wafer lot yy = year ww = work week 164 http://onsemi.com
mc100lve164 http://onsemi.com 2 q 32-lead lqfp (top view) nc a10 a9 a8 a7 a6 a5 nc nc sel3 vcc q sel2 sel1 sel0 nc a11 a12 a13 a14 a15 vcc nc nc a4 a3 a2 a1 a0 vee nc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 logic diagram and pinout assignment logic diagram a 0 a 1 a 14 a 15 sel0 sel1 sel2 sel3 q q 16:1 warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin function a 0 a 15 ecl data inputs sel[0:3] ecl select inputs q, q ecl differential outputs v cc positive supply v ee negative supply nc no connect function table sel3 sel2 sel1 sel0 data l l l l a0 l l l h a1 l l h l a2 l l h h a3 l h l l a4 l h l h a5 l h h l a6 l h h h a7 h l l l a8 h l l h a9 h l h l a10 h l h h a11 h h l l a12 h h l h a13 h h h l a14 h h h h a15
mc100lve164 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 to 0 v v ee necl mode power supply v cc = 0 v 8 to 0 v v i pecl mode input voltage v ee = 0 v v i v cc 6 to 0 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6o0 6 to 0 v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w q jc thermal resistance (junction to case) std bd 32 lqfp 12 to 17 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. lvpecl dc characteristics v cc = 3.3 v; v ee = 0.0 v (note 2) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 34 45 34 45 37 45 ma v oh output high voltage (note 3) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mv v ol output low voltage (note 3) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mv v ih input high voltage (single ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ended) 1490 1825 1490 1825 1490 1825 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 3. outputs are terminated through a 50 ohm resistor to v cc 2 volts. lvnecl dc characteristics v cc = 0.0 v; v ee = 3.3 v (note 4) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 34 45 34 45 37 45 ma v oh output high voltage (note 5) 1085 1005 880 1025 955 880 1025 955 880 mv v ol output low voltage (note 5) 1830 1695 1555 1810 1705 1620 1810 1705 1620 mv v ih input high voltage (single ended) 1165 880 1165 880 1165 880 mv v il input low voltage (single ended) 1810 1475 1810 1475 1810 1475 mv i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. input and output parameters vary 1:1 with v cc . v ee can vary 0.3 v. 5. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc100lve164 http://onsemi.com 4 ac characteristics v cc = 3.3 v; v ee = 0.0 v or v cc = 0.0 v; v ee = 3.3 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay a input to output sel0 sel1 sel2 sel3 350 500 400 400 400 600 700 675 675 550 850 900 900 900 700 350 500 400 400 400 600 700 675 675 550 850 900 900 900 700 350 500 400 400 400 600 700 675 675 550 850 900 900 900 700 ps t skew within device skew (note 7) 75 50 50 ps t jitter cycletocycle jitter tbd tbd tbd ps t r t f rise/fall times (20% 80%) 275 400 550 275 400 550 275 400 550 ps 6. v ee can vary 0.3 v. 7. within device skew is defined as the difference in the a to q delay between the 16 different a inputs. v tt = v cc 2.0 v figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100lve164 http://onsemi.com 5 package dimensions fa suffix lqfp package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc100lve164 http://onsemi.com 6 notes
mc100lve164 http://onsemi.com 7 notes
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